1. Field of the Invention
The present invention relates to a method of manufacturing liquid crystal displays, and more particularly, to a method for the planarization manufacturing of a high-transmittance liquid crystal display.
2. Description of the Related Art
There is an ever-increasing luminance requirement for products related to a liquid crystal display (LCD) available on the market, such as a desktop LCD, a notebook LCD, and an LCD TV. In order to meet the high-luminance requirement, LCD panel manufacturers envision an increase in the aperture ratio of LCD panels and the light transmittance of aperture areas in the hope of increasing the overall transmittance rate of LCD panels, but they are reluctant to pursue the goal at the expense of power consumption.
As regards the manufacturing processes and patents intended for high aperture ratios as put forth by TFT-LCD manufacturers in Japan and South Korea, they essentially involve overlapping data lines with transparent electrodes (a layer of Indium Tin Oxide, ITO), with the addition of an organic planarization layer on the upper surface after a passivation layer SiNx is done.
FIG. 1 is a schematic diagram about parts of a circuit for an active substrate disclosed by the specification of U.S. Pat. No. 5,883,682. On a substrate 111, there are a plurality of pixels 112 disposed at the intersections of a plurality of scanning lines (or gate lines) 115 and data lines 135. Furthermore, a gate pad 117 and a data pad (or a source pad) 137 are formed at one end of each scanning line 115 and each data line 135 respectively. Various driving devices are connected to the gate pads 117 and the data pads 137.
FIGS. 2(a)–2(e) are schematic diagrams about the steps of the manufacturing process for the cross-sectional structure taken along the line II—II in FIG. 1. As shown in FIG. 2(a), a conductive layer is formed first, and patterns of the gate pads 117, the scanning lines 115 and the gate electrodes 113 are defined on the substrate 111 in the photo-lithography process 1 (PEP1). A gate insulating layer 119, a semiconductor layer 121, a doped semiconductor layer 123 and a second conductive layer are overlaid on the combination of the substrate 111, the gate pads 117, the scanning lines 115 and the gate electrodes 113 respectively, overlapping each other. Then, during the photo-lithography process 2 (PEP2), patterns of the source electrodes 133, the drain electrodes 143, the data lines 135 and the data pads 137 are defined, and parts of the doped semiconductor layer 123 are removed in the light of the aforesaid patterns (as shown in FIG. 2(b)).
Although the gate insulating layer 119 is a transparent film made from materials like silicon nitrides (SiNx) and silicon oxides (SiOy), it reflects light and absorbs light energy. Hence, it is necessary to calculate and control the thickness of the film in order to ensure an optimal light transmittance.
As shown in FIG. 2(c), during the photo-lithography process 3 (PEP3), both the gate insulating layer 119 and the semiconductor layer 121 in the aperture areas are removed, but part of the semiconductor layer 121 around the gate electrodes 113 is kept in order to treat it as the channel for the thin film transistors 114, and at this point the gate pads 117 are totally exposed. Parts of the doped semiconductor layer 123, the semiconductor layer 121 and the gate insulating layer 119 are still found beneath the data pads 137.
An organic passivation layer 139 is deposited on the thin film transistors 114, the gate pads 117 and the data pads 137. Then, the photo-lithography process 4 (PEP4) is succeeding, and the through holes 161, 163 and 165 are disposed on the surface of the organic passivation layer 139, as shown in FIG. 2(d). The holes 161, 163 and 165 allow the drain electrodes 143, the gate pads 117 and the data pads 137 to be exposed out of the organic passivation layer 139.
Then, a transparent conductive layer is deposited on the organic passivation layer 139 and the holes 161, 163 and 165. During the photo-lithography process 5 (PEP5), the transparent conductive layer is patterned upon the mask, and the pixel electrodes 153, the gate pad terminals 157 and the pad terminals 177 are formed respectively.
The above described liquid crystal display requires at least one additional photo-lithography step for removing the gate insulating layer. Therefore, there is an urgent demand on the market for a manufacturing method that can save at least one photo-lithography process so as to produce a liquid crystal display with great competitiveness.